1. Field of the Invention
The present invention relates to a scan test circuit, a semiconductor integration circuit, and a scan enable signal time control circuit
2. Discussion of the Background Art
As a typical test for testing a semiconductor integration circuit, a SCAN/ATPG (Auto Test Pattern Generation) test is exemplified. When an At-Speed test (i.e., a test executed at an operation speed of a practical device) is executed during the SCAN/ATPG test, especially when a high-speed logic operation is executed, an At-Speed clock (a clock used in an operation speed of a practical device) is generated by driving a PLL circuit included in a LSI chip and is used in a capture operation of SCAN. Because, a frequency of a clock inputted from a LSI tester is limited by a ceiling.
Thus, a SCAN test circuit 101 that executes an At-Speed test by driving a PLL circuit included in a LSI chip generally has a configuration as shown in FIG. 3. A SCAN clock and a SCAN enable signal flowing the SCAN test circuit 101 have waveforms as illustrated in FIG. 4.
A control time as shown by the SCAN clock and the SCAN enable (signal) in FIG. 4 is called Broadside. Specifically, clocks, such as a launch clock 42, a capture clock 44, etc., entry twice when the SCAN enable is turned off (i.e., when a SCAN capture operation is executed).
During an interval between rises of the launch clock 42 and the capture clock 44, a test is executed at a practical operation speed, at which a practical device is operated. Test data are set to each of SCAN cells in synchronism with a rise of the launch clock 42. Test result is taken in to each of SCAN cells in synchronism with a rise of the capture clock 44. Since a SCAN enable signal inputted from a LSI tester is constant in this time period, a practical operation speed is not limited by a transition time period, i.e., from when the SCAN enable (signal) is turned on and off.
However, the Broadside needs clocks to set test data. Because, test data set by the launch clock 42 is controlled by data set to the SCAN cell by a last clock of a SCAN shift. Accordingly, to achieve malfunction detection at high percentage, a test pattern length and an ATPG execution time period generally become longer in comparison with a SCAN/ATPG (test) that detects single degeneracy malfunction.
Waveforms of a SCAN clock (signal) and a SCAN enable (signal) appearing in the SCAN test circuit when an SCAN/ATPG test is executed using a Launch-off-shift system are illustrated in FIG. 5. In such a Launch-off-shift system, test data are set to a SCAN cell in synchronism with a last clock of the SCAN shift as in the SCAN/ATPG test that detects single degeneracy malfunction. Thus, the ATPG execution time period and the test pattern length are generally as same as those in the SCAN/ATPG test that detects single degeneracy malfunction.
Specifically, in the Launch-off-shift system, an interval between the last clock of the SCAN shift (i.e., a launch clock 52) and the capture clock 54 represents a clock cycle for delay malfunction detection. Specifically, during the interval, a SCAN enable signal of the LSI tester needs to switch from turning on to off, and the clock cycle is thus limited. Accordingly, an At-Speed test (a practical operation speed), in which the PLL circuit of the LSI chip is driven, is hardly achieved.
The Japanese Application Laid Open No. 2001-221836 only discusses an integrated circuit testing method and apparatus that widely detects malfunctions using a short test length with a downsized hardware.
As mentioned above, when the Broadside system is used to apply the At-Speed test during the SCAN/ATPG test to the semiconductor integration circuit, both of the ATPG execution time period and the test pattern length become longer and costly. When it is attempted to decrease both of the ATPG execution time period and the test pattern length, the malfunction detection cannot be achieved at high percentage. Further, when the Launch-off-shift system is used, the At-Speed test cannot be executed, because of limitation on a SCAN enable signal caused by the LSI tester.